This disclosure relates to transistor switches, and more particularly to metal oxide semiconductor field-effect transistor (MOSFET) switches.
In power management ICs having a monolithically integrated MOSFET power train, the on-chip field-effect transistor (FET) not only accounts for most of the power dissipation, but also can consume a significant amount of silicon area, and very often is the major concern regarding the long-term reliability of the chip.
FIG. 1 shows a cross-sectional view of a conventional asymmetric high-voltage NMOS transistor, compatible with standard CMOS processes. Although implementations are described with reference to an asymmetrical NMOS device, other types of MOSFET devices are applicable.
An N+ source region 104 is formed within a P-type substrate 102. Also formed in P-type substrate 102 is an N-type deep drain (NDD) region 106 that includes an N+ drain implant 108, and an N-type lightly doped drain (LDD) implant 112. Also, formed upon P-type substrate 102 is a gate 114.
Two important dimensions in the device structure shown in FIG. 1 are the length LG of gate 114 and the length of the drain LD (e.g., the spacing between the N+ drain implant 108 and gate 114). Design rules for these two dimensions can be set to meet two specifications: punch-through breakdown voltage, and hot-carrier lifetime.
Quite often, the hot-carrier lifetime specification (also referred to as the reliability specification), instead of the punch-through breakdown voltage specification, determines the design rule which dictates the minimum allowed dimensions of LG and LD. In other words, in the applications where hot-carrier degradation is not of concern, a more aggressive design rule can be used to design a transistor such as that shown in FIG. 1 with smaller dimensions of LG and LD while still meeting the same punch-through breakdown voltage specification. A FET structure with smaller dimensions of LG or LD is generally preferred because such smaller dimensions not only reduce the overall chip area, but may also reduce the on-resistance and the junction capacitance of the FET, thus improving overall system efficiency.
Hot-carrier injection (HCI) typically occurs at the overlapping period between the transitions of the gate voltage and drain voltage of the FET, with the injection peaking when the gate voltage is approximately one half of the drain voltage. As a result, the typical inverter application turns out to be a stressful operation for a FET in terms of hot-carrier degradation. HCI is discussed in greater detail in W. Weber, C. Werner and A. V. Schwerin, “Lifetimes and substrate current in static and dynamic hot-carrier degradation”, IEDM 86, pp 390–393, 1986.
FIG. 2 shows a conceptual time t versus voltage v plot of voltage waveforms for a conventional N-FET during switching transitions of a typical inverter mode operation. During the turn-on transition, the drain voltage VD goes low and the gate voltage VG goes high. During the turn-off transition, VD goes high and VG goes low. The area between times t1 and t2 and t3 and t4 shows the transition period during which strong hot-carrier injection generally occurs. Hot-carrier degradation may result in threshold voltage shift and transconductance degradation of an N-FET. Due to hot-carrier degradation concerns, a conventional design of a FET switch typically involves trade-offs between electrical performance, such as on-resistance, and reliability performance, such as hot-carrier lifetime. In general, making a conventional device more resilient to hot-carrier degradation involves increasing one or both of LG and LD, while improving electrical performance (and minimizing device area) involves minimizing LG and LD.